Hereinafter, a conventional parallel type A/D converter will be described.
FIG. 7 is a diagram illustrating a conventional parallel type A/D converter 700 (for example, shown in FIG. 1 of Patent Document 1), and the A/D converter 700 comprises a comparison circuit 111, a coding circuit 112, and a clock buffer 122.
The operation of the conventional parallel type A/D converter, which is described in [Embodiment 1] in Patent Document 1, is as follows.
That is, an external input clock signal CKIN is input to the clock buffer 122, and the clock buffer 122 supplies an internal clock 203 synchronized with the external input clock signal CKIN to the comparison circuit 111 and to the coding circuit 112.
FIG. 8 shows timing charts of the comparison circuit 111 and the coding circuit 112 which are operated upon receipt of the external clock signal CKIN.
The comparison circuit 111 performs a comparison operation and the coding circuit 112 performs a reset operation during a first period T1 when the external input clock signal CKIN is at a first predetermined level V1, and the comparison circuit 111 performs a reset operation and the coding circuit 112 performs a coding operation during a second period T2 when the external input clock signal CKIN is at a second predetermined level V2. Thus, the operation of the conventional A/D converter 700 depends on the duty ratio of the external input clock signal CKIN.
Patent Document 1: Japanese Published Patent Application No. 2003-158456